A semiconductor memory device is under developing, which includes three-dimensionally disposed memory cells. For example, a NAND-type memory device includes a plurality of word lines stacked on a source line and a semiconductor pillar extending therethrough in the stacking direction. The memory cells are provided at portions respectively where the semiconductor pillar extends through the word lines. The semiconductor pillar is electrically connected to the source line, and acts as a channel body of each memory cells. The word lines act as control gates of the memory cells. Thus, the memory cells are operated respectively by a voltage between each of the word lines and the source line. In the device having such a structure, there may be a case where a voltage variation is increased due to a parasitic resistance of the source line, and results in a factor which induces a malfunction in the memory cells.